target depends upon a set of source files or even others targets described in Dependency List. A target most of time is a file to be created/updated. For instance, if your makefile is called run.mk then to execute make command type:Ī make file consists of a set of targets, dependencies and rules. The makefile often resides in the same directory as other source files and it can have any name you want. Make requires a makefile that tells it how your application should be built. It will be described later in this article.
target is a tag (or name defined) present in makefile. The main point is makefile structure and how it works. In this article an explanation of all those options are not in the scope. You can type make -help to see all options make command supports.
#Cuda c makefile example zip file#
There is a zip file with many samples in a directory structure.
#Cuda c makefile example how to#
This article is not a full tutorial, it focuses on C applications and how to use the make command and makefile to build them. The make command is used not only to help a developer compile applications, it can be used whenever you want to produce output files from several input files. The tool I'm talking about is the make command. However, when a project gets too complex with many source files it becomes necessary to have a tool that allows the developer to manage the project.
Developers can recompile them easily by calling the compiler directly, passing source files as arguments. Small C/C++ applications with a couple of modules are easy to manage.